Role Overview We are seeking a Physical Design Engineer with a strong foundation in Static Timing Analysis (STA) and a focus on design flow automation . In this role, you will be responsible for driving timing closure across complex, sub-nanometer process nodes while leveraging next-generation development tools. You will play a key role in developing, optimizing, and automating physical design workflows using Tcl and Python , incorporating AI-assisted development tools like GitHub Copilot to accelerate script delivery and engineering efficiency. Key Responsibilities Static Timing Analysis (STA): Execute timing signoff, constraint validation, multi-corner multi-mode (MCMM) analysis, and timing closure across all phases of physical implementation. Flow Automation & Scripting: Write, maintain, and enhance robust automated scripts using Tcl and Python to streamline EDA tool flows (place & route, synthesis, signoff). AI-Assisted Development: Utilize Copilot-assisted development tools to rapidly build, refactor, and test flow automation scripts, optimizing operational productivity. Timing & Power Optimization: Analyze setup/hold violations, crosstalk, IR drop, and clock path issues, collaborating closely with RTL and synthesis teams to achieve optimal PPA (Power, Performance, Area). Process Improvement: Standardize scripting frameworks, build continuous regression tests for physical design tools,



and document automated methodologies for the broader team. Qualifications Required Skills & Experience: Education: Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, Microelectronics, or a related field. Core STA Expertise: In-depth understanding of Static Timing Analysis principles, timing constraints (SDC), clock jitter, skew, cross-talk noise, and signoff methodologies using industry tools (e.G., Synopsys PrimeTime or Cadence Tempus). Scripting Proficiency: Strong hands-on coding ability in Tcl (for EDA tool integration) and Python (for data processing and workflow automation). Modern Development Tooling: Direct experience or strong familiarity with Copilot-assisted coding/script development tools (or LLM-driven coding tools) to write, debug, and optimize scripts efficiently. VLSI Fundamentals: Sound understanding of digital CMOS logic, place and route (PnR) flow fundamentals, and physical verification concepts. Preferred Qualifications: Experience with automated tool API integrations (e.G., Synopsys ICC2/Fusion Compiler, Cadence Innovus APIs). Experience implementing CI/CD pipelines or automated regression frameworks for hardware design flows. Background in Git or up-to-date version control systems for managing Tcl/Python script repositories.

📌 Physical Design Engineer (Toronto)
🏢 Cadence
📍 Toronto