Join Astera Labs as a Connectivity Verification Engineer and validate cutting-edge connectivity silicon for AI infrastructure. Utilize your expertise in UVM and C/C++ workflows to ensure product excellence.
In the role of Connectivity Verification Engineer, you'll play a vital role in enhancing AI systems through thorough verification processes. This position necessitates building verification environments, translating design specs into test strategies, and applying your skills in debugging and collaboration with RTL designers. Your contributions will shape the future of rack-scale AI infrastructure.
Key Responsibilities:
• Develop UVM verification environments utilizing SystemVerilog • Translate design specifications into actionable verification plans • Create comprehensive tests and analyze coverage data • Automate testing workflows using Python or Perl scripts • Collaborate with engineers to debug across simulations
Requirements: • Bachelor’s degree in Electrical Engineering or similar • 2-5 years of SoC or silicon product verification experience • Strong skills in SystemVerilog and UVM • Experience with directed and constrained-random testing • Eligible to work in Canada
Make an impact in AI connectivity validation as part of Astera Labs' creative team. #J-18808-Ljbffr