A specialist engineering consultancy supporting ASIC, FPGA, and embedded software development is expanding its team and is looking for aSenior FPGA Design Engineerto join a long-standing client engagement. You will work on-site with a global leader in optical and photonics technology, contributing to advanced, high-speed products at the forefront of optical networking and communications.This is a long-term opportunity for an experienced FPGA engineer who can ramp up quickly, take ownership of complex designs with minimal supervision, and grow into adesign primerole over the next couple of years. You will work closely with hardware, verification, and systems teams to take FPGA designs from specification and micro-architecture through implementation and timing closure.This is a full time, onsite position in Ottawa, and you should have full right to work in Canada.Key Responsibilities:Design and implement FPGA logic usingSystemVerilog, from micro-architecture through to production-ready, timing-clean designs.Analyze and manageclock domain crossings (CDC), including synchronization strategies and CDC verification.Own the FPGA synthesis flow, including tool configuration, timing constraints, and driving designs through to timing closure.Analyze synthesis and timing reports to identify and resolvetiming, congestion, and resource utilizationissues.Collaborate closely with hardware, verification, and systems engineering teams to ensure designs are robust, testable, and implementation-friendly.Participate in design reviews and technical documentation.Contribute to improving FPGA design methodologies, processes,



and best practices.Take increasing technical ownership with the chance to progress toward adesign primeposition.Key Qualifications:Approximately10–15 years of hands-on FPGA design experience, with the technical depth to ramp up quickly and take ownership of complex designs.Strong and current expertise inSystemVerilog .Practical experience identifying, analyzing, and resolvingclock domain crossing (CDC)challenges.Hands-on experience configuring and managingFPGA synthesis tools .Strong understanding ofSDC timing constraintsand constraint development.Proven ability to interpret synthesis and timing reports and translate findings into effective design changes.Experience taking FPGA designs through implementation and achievingtiming closure .Strong communication and collaboration skills across hardware, verification, and systems teams.Ability and willingness to workfull-time on-site in Ottawa, Canada .Legally eligible to work in Canada.Nice to Have:Exposure toUVM-based verification .Scripting experience withTcl, Python, or similar tools to automate and support FPGA design flows.Familiarity withhigh-speed interfacesused in optical networking, communications, or photonics products.The role offers a salary ofCAD $150,000–$170,000 per year, plus bonus and benefits, with final compensation dependent on experience and technical capability.By applying to this role you understand that we may collect your personal data and store and process it on our systems. For more information please see our Privacy Notice https://eu-recruit.Com/wp-content/uploads/2024/07/European-Tech-Recruit-Privacy-Notice-2024.Pdf#J-18808-Ljbffr

📌 Fpga Design Engineer – Fpga / Systemverilog / Cdc / Synthesis / Timing Closure / Digital Design (Varennes)
🏢 BTA Design Services
📍 Varennes