Shape the future of networking technology with Ciena as an ASIC Synthesis and STA Engineer. Lead the way in cutting-edge ASIC implementation processes with detailed timing verification and validation.

This role provides the opportunity to contribute to cutting-edge ASIC technology for high-speed connectivity. At Ciena, you will engage in frontend implementation tasks, including logical equivalence checking and clock domain crossing validation while collaborating closely with other engineering teams.

Key Responsibilities:
• Drive frontend implementation for assigned IP subsystems
• Maintain timing constraints for subsystem signoff
• Verify logical equivalence between RTL and netlists
• Validate clock domain crossings for top-level integration
• Create documentation to improve synthesis workflows

Requirements:
• B.Sc. in Electrical Engineering or equivalent
• Expertise in ASIC implementation and timing analysis
• Understanding of hardware description languages
• Strong teamwork and project management skills
• Ability to adapt to project schedules

Leverage your ASIC synthesis skills to make a difference at Ciena, a leader in optical networking.
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📌 ASIC Synthesis Engineer at Ciena (Quebec City)
🏢 Ciena
📍 Quebec City