Contribute to AI infrastructure innovations as a Senior Design Verification Engineer with Astera Labs. Focus on building scalable verification environments and leveraging C/C++ integration to drive verification success.
Astera
Labs is seeking a Senior Design Verification Engineer to enhance connectivity silicon for AI infrastructure. Your expertise will streamline the verification lifecycle and ensure high-quality products for up-to-date AI systems. Develop verification plans and reusable test sequences
- Write directed and constrained-random tests for robust validation
- Automate verification workflows using Python or Perl
- Bachelor’s in Electrical Engineering or related field
- Proficiency in SystemVerilog, UVM, and C/C++ verification
- Drive innovation in AI connectivity through strong verification skills at Astera Labs.
#
📌 Senior Design Verification Engineer at Astera Labs (Toronto)
🏢 Astera Labs
📍 Toronto
Reply to this offer
Impress this employer describing Your skills and abilities, fill out the form below and leave Your personal touch in the presentation letter.