Explore cutting-edge technology at Synopsys as a Digital Design Verification Intern in Mississauga, Ontario. Dive into real-world projects while learning essential skills in digital logic and verification methods. This 16-month co-op internship is ideal for engineering students pursuing hands-on experience in Digital Design Verification.

You will work on crucial tasks such as defining Verification Testplans and writing SystemVerilog testbenches. Collaborate with diverse teams and engage in cutting-edge projects that shape the future of ASIC design and verification within a hybrid working model. Key Responsibilities:
Define and track comprehensive Verification Testplans
Design and write SystemVerilog testbenches with UVM
Debug RTL and gate-level simulation failures
Conduct functional and code coverage analysis
Explore AI technologies in verification and ASIC design Requirements:
Bachelor’s degree in Computer or Electrical Engineering
Robust understanding of digital logic fundamentals
Familiarity with Verilog and SystemVerilog
Experience in scripting languages like Perl or Python
Willingness to learn and take responsibility Join Synopsys and advance your skills in digital design and verification.

📌 Digital Design Verification Internship Mississauga
🏢 Synopsys
📍 Mississauga