About Novacell

Novacell Solutions Inc. is a subsidiary of BTI Wireless Inc., a Los Angeles based company established in 1999. Novacell is concentrated on In Building Distributed Antenna System (DAS) Research and Development.

Job Overview

We are seeking a highly talented FPGA Design Engineer to join our engineering team. In this role, you will design, implement, and verify high-performance FPGA solutions for our next-generation Distributed Antenna Systems (DAS) and Wireless Coverage hardware. You will be responsible for digital signal processing (DSP) blocks, high-speed data interfaces, and system-on-chip (SoC) integration that powers real-time cellular communication (4G LTE, 5G NR, CBRS).

Given our global development footprint and manufacturing supply chain, this on-site position requires occasional flexibility to participate in early morning or late evening engineering syncs with international teams.

Responsibilities

- FPGA Architecture & Design: Architect, code (VHDL/Verilog/SystemVerilog), and implement FPGA logic for digital front-ends (DFE), filtering, digital up/down conversion (DUC/DDC), and RF signal routing algorithms.
- High-Speed Interface Integration: Implement and debug high-speed serial protocols and interfaces common in wireless infrastructure, such as CPRI/eCPRI, JESD204B/C (for data converters), PCIe, and Gigabit Ethernet.
- Timing Closure & Optimization: Perform synthesis, place-and-route, and timing closure on complex, multi-clock domain designs targeting major FPGA vendors (e.g., AMD/Xilinx, Intel/Altera).
- Verification & Simulation:



Develop comprehensive testbenches using ModelSim/QuestaSim or Vivado Simulator to perform pre- and post-layout simulations, validating functionality against RF system requirements.
- Hardware Bring-up & Lab Testing: Collaborate closely with hardware and RF engineers in the lab to bring up new boards, using oscilloscopes, logic analyzers, and spectrum analyzers to debug FPGA firmware on physical hardware.
- International Technical Collaboration: Interface with global R&D; teams, product managers, and software teams to align on system requirements, requiring occasional flexibility for off-hours international design reviews.

Qualifications

- Domain Expertise: 3+ years of experience in FPGA design and development, ideally with application experience in wireless communications, telecommunications infrastructure, digital signal processing (DSP), or RF systems.
- HDL Proficiency: Expert-level proficiency in VHDL, Verilog, or SystemVerilog for synthesis and simulation.
- Silicon Platform Knowledge: Deep hands-on experience with FPGA development suites (e.g., Xilinx Vivado, Intel Quartus Prime). Familiarity with SoC architectures (e.g., Zynq UltraScale+ MPSoC) is highly desirable.
- DSP Fundamentals: Strong grasp of digital signal processing concepts, including FIR/IIR filter design, Fast Fourier Transforms (FFTs),



and IQ modulation.
- Lab Skills: Proficient in hardware debugging and the use of standard laboratory test equipment (logic analyzers, high-speed oscilloscopes, signal generators).
- Location & Flexibility: Ability to work full time on-site at our engineering laboratory, with the scheduling flexibility needed to support occasional global engineering alignments.

Pay: $75,000.00-$110,000.00 per year

Benefits

- Company events
- Dental care
- Disability insurance
- Extended health care
- Life insurance
- In office parking
- Paid time off
- RRSP match

Ability to commute/relocate:
- Richmond, BC: reliably commute or plan to relocate before starting work (required)

Application question(s):
- Do you hold a Bachelor's degree (or higher) in Electrical Engineering, Computer Engineering, Computer Science, or a related technical field?
- Are you comfortable working a full-time on-site schedule with the flexibility to occasionally join early morning or late evening technical syncs with international engineering teams?
- Are you currently located in Richmond, or able to work full-time on-site at our engineering laboratory?
- Do you have experience designing and debugging high-speed wireless interfaces and protocols (e.g., CPRI/eCPRI, JESD204B/C, PCIe) or RF digital front-end (DFE) logic?

Education:
- Bachelor's Degree (required)

Experience:
- FPGA design using VHDL, Verilog, or SystemVerilog: 3 years (required)
- major development suites (such as Xilinx Vivado etc.): 3 years (required)

Work Location: In person

📌 FPGA Design Engineer (Wireless Infrastructure & DAS) (Richmond)
🏢 Nova Cell
📍 Richmond