Senior Rtl/Fpga Design Eng - Verilog, Vivado, Cdc (Contract) - C$110 - C$135 An Hour (Boucherville)

Senior Rtl/Fpga Design Eng - Verilog, Vivado, Cdc (Contract) - C$110 - C$135 An Hour (Boucherville)

14 Sep
|
LanceSoft
|
Boucherville

14 Sep

LanceSoft

Boucherville

Seeking an experienced RTL/FPGA Design Engineer for a contract role in semiconductor design, requiring Verilog, System Verilog, and EDA tool proficiency.

📌 Senior Rtl/Fpga Design Eng - Verilog, Vivado, Cdc (Contract) - C$110 - C$135 An Hour (Boucherville)
🏢 LanceSoft
📍 Boucherville

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