Join Ciena as an ASIC Synthesis and STA Engineer, shaping the future of high-speed connectivity. Drive cutting-edge solutions in front-end ASIC implementation with a focus on synthesis and timing analysis. In this critical role at Ciena, you will execute frontend implementations for IP subsystems, ensuring successful synthesis, static timing analysis, and clock domain checks.
Contributing to the development of industry-leading ASIC technology, you will collaborate with multidisciplinary teams to align frontend and backend activities seamlessly. Key Responsibilities:
- Execute frontend implementation for assigned IPC subsystems
- Develop and maintain timing constraints for integration
- Perform logical equivalence verification of RTL and gate-level netlists
- Validate clock domain crossings for ASIC integration
- Optimize scripts and tools to enhance workflows Requirements:
- B.Sc. in Electrical/Computer Engineering or equivalent
- Knowledge of ASIC implementation flows
- Familiarity with RTL design principles
- Effective team collaboration skills
- Ability to manage deliverables to schedules Make an impact in high-performance optical networking at Ciena through your ASIC synthesis and timing analysis expertise.