Elevate ASIC design with Cisco as a Senior Technical Leader. Spearhead fullchip floorplan design and enhance methodologies to impact the AI era through cutting-edge hardware solutions.

Join Cisco’s Common Hardware Group, where you'll leverage over 12 years of experience in Physical Design. This role focuses on RTL-to-GDSII implementation and requires proficiency in low-power methodologies using UPF. Collaborate with cross-functional teams to define signoff methodologies, utilizing cutting-edge tools to optimize performance, power, and die size.

Key Responsibilities:
• Design fullchip floorplans considering architecture and constraints
• Collaborate on requirements with system design teams
• Execute hierarchical implementation flow and clock planning




• Analyze tool flows for efficiency improvements
• Interface with vendors for best-in-class design methodology

Requirements:
• Bachelor’s with 12 years, Master’s with 8 years of experience
• Proven experience in Fullchip activities
• Expertise in RTL-to-GDSII flows for 7nm process technologies
• Familiar with EDA tools like Innovus and Primetime
• Experience with AI tools for productivity improvements

Drive ASIC design forward, optimize methodologies, and shape the future at Cisco.
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📌 Senior ASIC Development Leader at Cisco (British Columbia)
🏢 CISCO
📍 British Columbia