Synopsys Inc. seeks an enthusiastic ASIC Digital Design Verification Engineer to verify Interface IP protocols and drive robust verification environments. You will collaborate with design teams to identify and fix issues, develop comprehensive test plans, and mentor junior engineers in contemporary verification methodologies. As part of a dynamic team, you will apply SystemVerilog, UVM, and SVA to deliver high-quality IP solutions, documenting results and participating in reviews to ensure overall
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📌 Senior ASIC Verification Engineer - Interface IP & UVM Lead (Winnipeg)
🏢 Synopsys
📍 Winnipeg
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