Contribute to AI infrastructure innovations as a Senior Design Verification Engineer with Astera Labs. Focus on building scalable verification environments and leveraging C/C++ integration to drive verification success.

Astera

Labs is seeking a Senior Design Verification Engineer to enhance connectivity silicon for AI infrastructure. This key role involves partnering with RTL designers and developing UVM-based verification environments using SystemVerilog. Your expertise will streamline the verification lifecycle and ensure high-quality products for modern AI systems. Key Responsibilities:

- Build UVM-based verification environments with SystemVerilog integration
- Develop verification plans and reusable test sequences




- Write directed and constrained-random tests for robust validation
- Automate verification workflows using Python or Perl
- Collaborate with RTL designers to debug and resolve issues Requirements:
- Bachelor’s in Electrical Engineering or related field
- 2-5 years in complex SoC or silicon verification
- Proficiency in SystemVerilog, UVM, and C/C++ verification
- Experience with verification infrastructure development
- Authorized to work in Canada Drive innovation in AI connectivity through robust verification skills at Astera Labs.

📌 Senior Design Verification Engineer at Astera Labs (Toronto)
🏢 Astera Labs
📍 Toronto