Serdes Technology Group develops high-performance, multi-protocol wireline transceivers in state-of-the-art CMOS process.
We are currently seeking an analog/mixed-signal designer to work on analog and mixed-signal building blocks in wireline transceivers.
The candidate will be responsible for
Own and execute analog/mixed-signal design of blocks, such as low-dropout regulators (LDOs), bandgap circuits, analog bias circuits, amplifiers, clocking circuits, ADCs and DACs.
Port schematics into current technology nodes (Ex. from N3 to N2)
Implement and optimize circuits for meeting the defined block specifications and functionality requirements
Guide the layout designer(s) to implement the layout of the circuit blocks,
and manage the quality of layout and floorplan of the circuit blocks
Perform pre-layout (schematic) simulations and post-layout simulations
Deliver the design reviews based on SerDes team’s design methodology and design review requirements
EXPERIENCE AND EDUATION
5-7 years of relevant work experience;
Experience with Schematic Design and Circuit Simulation in Cadence Virtuoso
Experience in circuit reliability and EMIR verification of analog/mixed signal blocks
Experience in advanced CMOS process technology nodes (N7,N6, N5, N3, N2...etc) is preferred