Design GRAPHICS CORE IP THE TEAM: Graphics Core IP develops the digital design and verification logic behind GPU graphics and compute capabilities. The team works from architecture guidance to implement, debug, and close RTL for complex GPU blocks, collaborating closely with architecture, verification, physical design, power, project management, and post-silicon teams. This role is intended for a design engineer who can work within an existing RTL codebase, understand the surrounding design intent, and implement well-scoped features with strong attention to quality, maintainability, and schedule.

The immediate team is a focused subsystem design and verification group with engineers across different levels of experience.

DESIGN ENGINEER THE ROLE: As a Design Engineer, you will modify and extend existing RTL for Graphics Core IP blocks. The work will focus on targeted feature additions, cleanup, and quality improvements such as medium-grain clock gating, performance counters, debug bus support, simple control/status logic, and related integration updates. You will work closely with senior design engineers, architects, verification, physical design, and power teams to deliver correct, reviewable RTL changes that integrate cleanly into the broader GPU design.

THE PERSON: The ideal candidate has strong digital design fundamentals, is comfortable reading and modifying existing Verilog/SystemVerilog code, and can debug issues methodically. They should be detail-oriented, cooperative, and able to take ownership of well-defined design tasks while asking good questions when requirements or design intent are unclear. KEY RESPONSIBILITIES:

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Understand relevant architecture and micro-architecture specifications for assigned Graphics Core IP blocks

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Modify existing RTL to implement targeted features such as clock gating, performance counters, debug bus support, and simple control/status logic

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Write clean, maintainable Verilog/SystemVerilog and update related assertions or checks where needed

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Debug simulation failures, review waveforms, and work with verification engineers to close issues

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Collaborate with design, verification, physical design, and power teams to ensure changes meet functional, timing, power, and integration requirements

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REQUIREMENTS

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Solid understanding of digital design and computer architecture fundamentals

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Hands-on experience with Verilog or SystemVerilog RTL design

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Ability to read, modify, debug, and maintain existing design code

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Familiarity with simulation and debug tools such as VCS, ModelSim, Verdi, waveform viewers, or equivalent tools

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Basic scripting ability in Perl, Tcl, Python, Bash, C-shell, or similar

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Strong analytical skills, attention to detail, and clear written and verbal communication GROWTH OPPORTUNITIES:

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Gain hands-on experience in GPU RTL design and integration

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Build practical expertise in Verilog/SystemVerilog, simulation debug, assertions, and design-quality practices

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Learn how performance, power, timing, and debug requirements are implemented in production GPU designs

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Work with experienced engineers and industry-standard design and verification tools ACADEMIC CREDENTIALS:

- Bachelor’s Degree in Computer, Electrical, Mechatronics Engineering or Engineering Science or similar LOCATION: Markham, ON Canada

📌 Engineering - ASIC/RTL Design Engineer 4 (Markham)
🏢 Mindlance
📍 Markham