Elevate your career as a Lead Digital Verification Engineer with Ciena. This role focuses on validating creative FEC architectures and leading a team in the telecommunications industry.

Ciena is seeking a talented engineer to enhance the Wavelogic modem family. With over 10 years of verification experience, you will develop test plans, validate functional blocks, and mentor junior engineers. Your communication skills will facilitate collaboration with designers and systems engineers, ensuring high-quality results in a fast-paced environment.

Key Responsibilities:



• Develop functional coverage and verification test plans • Validate FEC functional blocks via simulation and formal methods • Create components and scenarios using System Verilog UVM and C++ • Monitor regressions and debug with designers' support • Provide status updates on verification progress

Requirements: • 10+ years of verification experience • Bachelor's degree in Electrical or Computer Engineering • Expertise in C/C++, System Verilog, and simulators • Proven leadership in fostering a culture of innovation • Strong decision-making and problem-solving skills

Drive the future of networking by shaping verification strategies at Ciena. #J-18808-Ljbffr

📌 Lead Digital Verification Engineer at Ciena (Montreal)
🏢 Ciena
📍 Montreal