Job Title: Design Verification Engineer Client: NeurealM/ Microchip Location: Vancouver, BC, Canada - Initial 1 month Hybrid then after Remote Job Type: Contract Job Summary We are looking for aDesign Verification Engineerwith robust experience inASIC/SoC verificationto develop and execute verification environments and ensure high-quality digital designs.

Responsibilities Develop verification environments and testbenches using

System

Verilog and UVM.

Create and execute functional, regression, and constrained-random tests.

Analyzefunctional/code coverageand drive coverage closure.

Debug RTL and simulation failures and work with design teams to resolve issues.

Verify protocols such asAMBA/AXI, PCIe, Ethernet, or similar interfaces.

Automate testing and regression using

Python, Perl, or Shell scripting.

Required Skills Robust

System

Verilog & UVMexperience.

Solid understanding ofRTL, digital design, and ASIC/SoC verification.

Experience with simulation tools such asVCS, Xcelium, or Questa.

Robust debugging and scripting skills.

Bachelor''s/Master''s degree in

Electrical, Electronics, or Computer Engineering.

📌 Design Verification Engineer Vancouver (Canada)
🏢 Diligent Tec
📍 Canada