As the global leader in high-speed connectivity, Ciena builds the critical infrastructure powering the AI era. We’re a technology company shaping the future of networking, guided by innovation, integrity, and collaboration. Through development opportunities, meaningful work, and flexibility, Ciena supports growth and well-being—on and off the job. Connect with a career that matters.The Prospect:Work term of 4 months starting in Spetember/October 2026.The WaveLogic™ family of products is a cornerstone of Ciena’s optical fiber transmission solutions and a key contributor to the company’s leadership in the global telecommunications industry. This opportunity provides hands‑on exposure to advanced high-speed analog and mixed‑signal circuit design within a team that has contributed to more than three decades of innovation in broadband fiber‑optic modems. The role offers the opportunity to contribute to next‑generation high‑speed circuit development in a collaborative engineering environment.How you will make an impact:Contribute to layout feasibility studies in partnership with senior analog designers, evaluating design trade-offs and layout strategies for high-speed circuitsDevelop custom layouts for advanced analog and mixed‑signal blocks, following structured methodologies for floorplanning, placement, and routingExecute comprehensive physical verification, including design rule checks (DRC), layout versus schematic (LVS), electromigration (EM), and infrared (IR) drop analysis to ensure layout quality and reliabilityExplore new layout tool features, flows, and processes to enhance efficiency and productivityCollaborate closely with circuit designers and layout engineers to identify and resolve layout‑related risks early in the design cycleProvide clear status updates and participate in team meetings, design discussions, and knowledge‑sharing activitiesThe must haves:Education:



Actively enrolled in a degree program in Electrical Engineering or a related field,Hands‑on experience with custom analog and mixed‑signal layout design in deep sub‑micron complementary metal‑oxide semiconductor (CMOS) technologiesStrong understanding of layout techniques, including floorplanning, device matching, parasitic minimization, shielding, electromigration, and IR drop considerationsExperience creating custom layouts for analog or mixed‑signal blocks such as operational amplifiers or current mirrorsFamiliarity with semiconductor manufacturing processes and foundry design rulesExperience using industry-standard layout tools such as Cadence Virtuoso and Siemens CalibreAbility to interpret and debug DRC and LVS reports effectivelyNice to haves:Exposure to high-speed data converter or phase‑locked loop (PLL) layout designFamiliarity with bipolar CMOS (BiCMOS) technologiesScripting experience using PERL or SKILL to support layout automation or productivity improvementsExperience collaborating in cross‑functional hardware design teamsStrong analytical skills with the ability to proactively identify layout‑sensitive circuit structuresPay Range:The hourly pay rate for this position is $25.50 – $35.00Pay ranges at Ciena are designed to accommodate variations in knowledge, skills, experience, market conditions, and locations, reflecting our diverse products, industries, and lines of business. Please note that the pay range information provided in this posting pertains specifically to the primary location, which is the top location listed in case multiple locations are available.In addition to competitive compensation, Ciena offers students access to the Employee Assistance Program (EAP), company‑paid holidays, paid sick leave, and vacation pay as required by applicable laws.At Ciena, we are committed to building and fostering an environment in which our employees feel respected, valued, and heard. Ciena values the diversity of its workforce and respects its employees as individuals. We do not tolerate any form of discrimination.Ciena is anEqual Opportunity Employer, including disability and protected veteran status.If contacted in relation to a job opportunity, please advise Ciena of any accommodation measures you may require.#J-18808-Ljbffr

📌 Electrical Design Engineer Ii (Boucherville)
🏢 Ciena
📍 Boucherville