As a member of the Mixed‑Signal Development Group, the candidate will be engaged in the support and debugging of PLLs, high‑speed SERDES, ADCs, DACs, and other analog building blocks.ResponsibilitiesDefine the requirements for Mixed‑Signal IPs in discussion with the SoC architectsCollaborate with IP vendors to customize IP solutions and finalize Statement of Work (SOW)Manage IP intake processes, including pre‑licensing and post‑acquisition QA, integration, and sign‑off reviewsSupport Mixed‑Signal IP through post‑tape‑out phase, including lab testing, customer bring‑up and debugActive involvement in lab testing, support and debug of mixed‑signal and SERDES blocksOwnership of circuit and system specificationsDesign CMOS analog and mixed‑signal integrated circuitsRequirements / QualificationsBachelor’s degree in electrical engineering or related field with strong analog/mixed‑signal background and at least 10 years of mixed‑signal CMOS circuit design experience,



or a Master’s degree with at least 7.5 years of such experienceDeep understanding of the mixed‑signal analog design flow steps including architecture, design, and integrationExperience with high‑speed SERDES and/or PLL circuitsExperience with circuit simulators (HSPICE, Spectre, etc.)Experience working with PCIe, SAS, SATA and Ethernet protocols is a plusExperience working with chiplet technologies is a plusPossess understanding of device physics and basic ESD/Latch‑up conceptsStrong written and oral communication skillsAbility to work in a team environmentInnovative and creative thinkerAbility to quickly ramp on new projectsBenefitsTravel Time: 0% – 25%Pay Range: $86,000 – $186,000. The range depends on factors such as location, skills, and experience.We offer a comprehensive benefits package that includes health perks that begin day one, retirement savings plans, and an industry leading IESPP program.#J-18808-Ljbffr

📌 Principal Engineer - Analog/Mixed-Signal (Ip Technical Lead) (Burnaby) - C$86,000 - C$186,000 A Year
🏢 Microchip Technology
📍 Winnipeg