Cisco Systems Canada Co. in Vancouver is seeking a seasoned Physical Design engineer to lead fullchip floorplanning, IP placement, clock planning, and signoff methodologies. You will collaborate across RTL/DFT/EDA teams to optimize timing, power integrity, and die size while leveraging AI tools to boost productivity. The role requires deep experience with RTL-to-GDSII flows, hierarchical design, and close interaction with foundries and IP vendors to ensure robust signoff.
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📌 Senior ASIC Physical Design Lead – Fullchip (Winnipeg)
🏢 105 Cisco Systems Canada
📍 Winnipeg
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