Drive innovations as the Lead Memory Layout Engineer at Infosys, stationed in Vancouver, BC. Your role focuses on design optimization in memory arrays and layouts.

You will be integral to collaborating with design engineers in creating superior memory layouts based on schematic designs. This position calls for extensive experience in Compiler and Memory Layout processes, with a keen eye for optimized performance characteristics.

By utilizing advanced FinFET technology, you will ensure the adherence to DRC limitations while exploring current layout prospects.

Key Responsibilities:
Collaborate to refine memory layout designs
Create top-level memory leafcell layout libraries
Implement memory architecture best practices




Conduct comprehensive physical verification and debugging
Engage in cross-team collaboration to finalize designs

Requirements:
5+ years of relevant memory layout design experience
Bachelor’s degree or equivalent in a technical discipline
Expertise in Cadence Virtuoso and verification tools
Familiarity with advanced layout technologies, including 3nm
Must be based in or willing to relocate to Vancouver, BC

Bring your leadership in memory layout design to Infosys and shape the future of technology.
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📌 Lead Memory Layout Engineer At Infosys Burnaby
🏢 Infosys
📍 Burnaby