Seeking an ASIC Design Engineer for a Canadian startup to design digital circuits for optical transceivers, optimize performance, and integrate designs with teams. Requires Verilog/System Verilog proficiency.
📌 Senior Asic Design Engineer – Verilog/Ppa Expert - C$150,000 - C$250,000 A Year (Boucherville)
🏢 Semiconductor Startup
📍 Boucherville
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