Seeking an experienced ASIC Verification Engineer for a semiconductor startup in Ottawa to develop verification plans and ensure ASIC design functionality and reliability. Requires 3+ years of experience and proficiency in Verilog, SystemVerilog, and UVM.
📌 Senior Asic Verification Engineer - C$150,000 - C$250,000 A Year (Varennes)
🏢 Semiconductor Start-Up
📍 Varennes
Reply to this offer
Impress this employer describing Your skills and abilities, fill out the form below and leave Your personal touch in the presentation letter.