Seeking an ASIC Design Engineer for a Canadian semiconductor startup to design digital circuits for optical transceivers, optimizing performance and collaborating on integration. Requires an Electrical Engineering degree and 3 years of digital design experience with Verilog/System Verilog.
📌 Senior Asic Design Engineer – Verilog/Ppa Expert - C$150,000 - C$250,000 A Year (Varennes)
🏢 CELERO COMMUNICATIONS
📍 Varennes
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