Seeking an experienced ASIC Design Engineer in Toronto to translate requirements into architecture specifications and design complex RTL logic. Must be proficient in Verilog/System Verilog and system-level troubleshooting.
📌 Senior Asic Design Engineer – Rtl, Synthesis & Ai/Hpc Socs - C$140,000 - C$190,000 A Year (Toronto)
🏢 Technology Design
📍 Toronto
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