Cisco Systems Canada Co. in Vancouver is seeking a seasoned Physical Design engineer to lead fullchip floorplanning, IP placement, clock planning, and signoff methodologies.
You will collaborate across RTL/DFT/EDA teams to optimize timing, power integrity, and die size while leveraging AI tools to boost productivity. The role requires deep experience with RTL-to-GDSII flows, hierarchical design, and close interaction with foundries and IP vendors to ensure robust signoff.
#J-18808-Ljbffr
📌 Senior ASIC Physical Design Lead – Fullchip (British Columbia)
🏢 105 Cisco Systems Canada
📍 British Columbia
Reply to this offer
Impress this employer describing Your skills and abilities, fill out the form below and leave Your personal touch in the presentation letter.