Engineering Group, Engineering Group ASICS Engineering As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives communication and data processing transformation to help create a smarter, connected future for all. As a Qualcomm ASIC Engineer, you will define, model, design (digital and/or analog), optimize, verify, validate, implement, and document IP (block/SoC) development for a variety of high performance, high quality, low power world class products. Bachelor's degree in Science, Engineering, or related field and 6+ years of ASIC design, verification, validation, integration, or related work experience.

Master's degree in Science, Engineering, or related field and 5+ years of ASIC design, verification, validation, integration, or related work experience. PhD in Science, Engineering, or related field and 4+ years of ASIC design, verification, validation, integration, or related work experience. Qualcomm is expanding its team in connectivity networking products engineering Team.

We are looking for experienced SoC RTL design engineers to contribute to our next generation connectivity networking products. This is an incredible opportunity to be part of the AI revolution and contribute to the complete semiconductor development cycle, from concept to product. The ideal candidate will have a robust and extensive background in RTL design across multiple projects.

As an experienced RTL Design Engineer, you will work in SoC design and SOC-Subsystem design. You will be responsible for microarchitecture/RTL coding of the SOC/subsystems and create microarchitecture documents. You will work with Physical design team to meet area, power and performance goals.

You will support physical design teams, verification teams, software teams and FPGA teams to ensure high quality SoC and ensure successful tapeout. Products purpose-built for AI datacenter scale out and scale up connectivity Work alongside some of the best minds in the semiconductor industry.



Micro architect and RTL Design of SoC SubSystem/IP blocks Will be responsible for RTL quality checks - Lint/CDC/LEC Responsible for analyse / debug / fixing issues reported by verification team Work with SOC Architect/Leads to integrate the design, review/sign-off verification plan, DFT and PD implementation Strong background with multi-year and multi-project experience in RTL SoC Design (Verilog/VHDL), and ASIC/FPGA debug methodologies Test Plans & Verification: Proficient in reviewing high-level test plans and coverage metrics.

Expertise in Design Compiler Synthesis and formal verification using LEC.

Bus Protocols & Peripherals: Knowledge of bus protocols such as AHB, AXI, and peripherals like PCIe, USB, Ethernet, etc.

Chip IO Design: Knowledge of chip IO design and packaging is beneficial. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail [email protected] request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process.

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📌 RTL Design Engineer, Sr Staff (Toronto)
🏢 Qualcomm
📍 Toronto