Execute frontend ASIC implementation, including synthesis and static timing analysis, for high-speed connectivity. Collaborate with cross-functional teams and EDA partners. Develop timing constraints and validate clock domain crossings.
📌 Senior Asic Synthesis And Sta Engineer - C$109,000 - C$174,000 A Year (Boucherville)
🏢 Ciena
📍 Boucherville
Reply to this offer
Impress this employer describing Your skills and abilities, fill out the form below and leave Your personal touch in the presentation letter.