Seek an impactful role as a Memory Layout Engineer with specialized skills in advanced node technologies for semiconductor applications. Focus on memory layout design and verification with TSMC's leading-edge processes.

In this position, you will be responsible for custom layouts and physical verification of memory architectures, including critical SRAM components. Your hands-on experience will enable you to conduct top-level integration and manage issues related to layout quality. Working alongside cross-functional teams, you will enhance performance and efficiency in semiconductor designs.

Key Responsibilities:
• Create and implement layouts for memory architectures
• Optimize designs for key memory components
• Conduct seamless top-level memory integration




• Execute DRC, LVS, and density verification checks
• Address IR drop and Electromigration challenges effectively

Requirements:
• Bachelor's/Master's degree in Electrical/Electronics Engineering
• Proven track record in advanced layout design
• Direct experience with TSMC 7nm processes
• Proficient in industry-standard verification tools
• Solid analytical skills for layout troubleshooting

Apply your expertise in memory layout and verification to drive excellence in semiconductor design.
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📌 Expert Memory Layout Engineer Role (Quebec City)
🏢 Odyssey Global
📍 Quebec City