Become the Memory Layout Design Lead at Infosys, working remotely or locally in Vancouver, BC. Use your expertise to advance memory management and layout design practices.

In this pivotal role, you will contribute to layout and design projects alongside top engineers, focusing on optimizing memory arrays and creating creative layouts from schematics. Your hands-on experience in FinFET technologies and various memory architecture types will significantly enhance the performance and quality of projects.

This role aims to push the boundaries of technical design to deliver superior outcomes.

Key Responsibilities:
Design and implement memory layouts in collaboration with circuit engineers
Oversee the creation of layout libraries from scratch




Ensure designs adhere to performance optimization standards
Engage in thorough physical verification processes
Work closely with cross-functional teams to assure design integrity

Requirements:
5+ years in Compiler/Custom Memory Layout design
Bachelor's degree or related experience is necessary
Proficient in Cadence tools and physical verification strategies
Exposure to advanced technologies like 3nm or 5nm
Located near Vancouver, BC, or willing to relocate

Elevate the performance of memory technologies and layouts at Infosys, making your mark on the industry.
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📌 Infosys Memory Layout Design Lead Burnaby
🏢 Infosys
📍 Burnaby