Advance your career as an ASIC Synthesis and Static Timing Engineer with Ciena, the forefront of high-speed connectivity. Engage in critical front-end activities like synthesis and clock validation.

In this role, you will be instrumental in the front-end implementation of cutting-edge ASIC technology. Your expertise will contribute to synthesizing assignments and ensuring logical equivalence within complex systems. Ciena offers a collaborative workplace to engage effectively with various engineering disciplines and external partners alike.

Key Responsibilities:
• Develop frontend implementation for assigned ASIC IP subsystems
• Manage timing constraints for synthesis and subsystem integration




• Conduct logical equivalence verification pre and post-layout
• Validate clock domain crossings to ensure design integrity
• Create scripts to improve synthesis workflows

Requirements:
• Bachelor’s degree in a related engineering field
• Comprehensive knowledge of ASIC flows and timing analysis tools
• Experience with RTL design principles
• Proven teamwork in multidisciplinary projects
• Ability to maintain project schedules

Leverage your ASIC skills at Ciena while contributing to the future of networking.
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📌 Ciena ASIC Synthesis and Timing Engineer (Quebec City)
🏢 Ciena
📍 Quebec City