Principal Physical Design Methodology Engineer Date Posted Synopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leading silicon design, IP, simulation and analysis solutions, and design services. We partner closely with our customers across a wide range of industries to maximize their R&D; capability and productivity, powering innovation today that ignites the ingenuity of tomorrow.

You have spent a decade building the kind of high-speed digital IP that actually ships in products people use, and you know the difference between a flow that looks good in a deck and one that survives contact with a 3nm tapeout schedule. You have opened Fusion Compiler or ICC2 enough times that you know where the tools break down, and you have written enough Tcl and Python to automate your way around those edges. Lead the digital methodology engineering effort for Interface IP, defining and maintaining the complete RTL-to-GDSII implementation flow using Fusion Compiler, PrimeTime, PrimePower, and related Synopsys toolchains Build, test, and deploy synthesis and place-and-route methodologies for high-speed IP cores and subsystems targeting advanced nodes (5nm, 3nm, and beyond) Evaluate and optimize design-for-test insertion, timing closure, power optimization, and EM/IR analysis workflows across multiple IP development teams Act as the technical bridge between EDA tool development teams and IP design teams,



translating tool capabilities into usable methodology and feeding real-world design challenges back to tool teams Mentor engineers across global teams on digital implementation best practices, timing closure strategies, and physical design tradeoffs Drive continuous improvement of design processes by identifying bottlenecks, proposing solutions, and measuring impact on PPA and schedule Your methodologies will directly determine the PPA outcomes for Synopsys Interface IP products used by semiconductor companies worldwide You will enable IP teams to adopt new process nodes and EDA tool versions with confidence, reducing risk and accelerating time to tapeout Engineers you train will carry forward the practices you establish, multiplying your impact across dozens of projects and hundreds of tapeouts The automation and reference flows you create will become the foundation for how Synopsys develops high-speed digital IP for years to come You will help Synopsys maintain its position as the provider of best-in-class IP by ensuring every design starts with a world-class implementation methodology Bachelor's or Master's in Electrical Engineering or Computer Engineering with 10+ years of hands-on ASIC digital implementation experience Deep expertise with Fusion Compiler or equivalent industry synthesis and place-and-route tools (ICC2, Innovus), including advanced features like multi-mode multi-corner optimization,



clock tree synthesis, and physical synthesis Proven track record developing or supporting high-speed digital IP cores or SoCs, ideally in SerDes, memory controllers, or similar high-performance designs Solid scripting skills in Tcl and Python for flow automation, analysis, and reporting Experience with Synopsys timing and power analysis tools like PrimeTime, PrimePower, RLTA, or CoreTools is a strong plus You can explain a complex PPA tradeoff to a design lead in two sentences without losing the technical nuance, and you can explain the same tradeoff to a tool developer in the level of detail they need to act on it You will join the Interface IP Digital Design Methodology team, a global group responsible for defining and maintaining the ASIC design standards and flows that support Synopsys IP development teams.

This team works directly with next-generation SerDes and memory interface controllers, PHYs, and subsystems, and collaborates closely with both IP design teams and EDA tool development teams across North America, Europe, and Asia. You will be part of a technical community that values deep expertise, practical problem solving, and the kind of collaboration that happens when engineers respect each other's work.

Synopsys

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📌 Principal, R&D Engineering (Markham)
🏢 Synopsys
📍 Markham