Explore a pivotal front-end ASIC Engineer role with Ciena, a leader in high-speed connectivity. Immerse yourself in ASIC technology through synthesis, static timing analysis, and validation.
This position focuses on shaping the front-end implementation of industry-leading ASIC technology. Ciena seeks a knowledgeable engineer to execute synthesis, maintain timing constraints, and ensure functional integrity. Collaborate with multidisciplinary teams focused on both frontend and backend activities to deliver exceptional results.
Key Responsibilities:



- Execute synthesis and static timing analysis for assigned IP subsystems - Maintain timing constraints for subsystem integration signoff - Perform logical equivalence verification between RTL and gate-level netlists - Validate clock domain crossings for top-level ASIC integration - Optimize scripts and tools to enhance workflows
Requirements: - B.Sc. in Electrical or Computer Engineering - Knowledge of ASIC implementation flows and timing analysis - Familiarity with RTL design and hardware description languages - Effective collaboration within engineering teams - Ability to manage project deliverables
Shape the future of optical networking with Ciena through your ASIC expertise.#J-18808-Ljbffr

📌 Front End Asic Engineer At Ciena Riviere Des Prairies—pointe Aux Trembles (Canada)
🏢 Ciena
📍 Canada