Join a cutting-edge team as a Memory Layout Engineer specializing in advanced node technologies for high-performance semiconductor designs. Leverage expertise in TSMC FinFET processes to push boundaries in memory layout development.

This role requires a highly skilled engineer to design custom layouts for memory blocks, optimize critical components, and perform top-level memory integration. Your hands-on experience with physical verification and layout cleanup will ensure high-quality outcomes. Collaboration with circuit, physical design, and process teams is integral to achieving optimal performance.

Key Responsibilities:



• Design custom memory layouts across multiple architectures • Optimize layouts for SRAM and critical memory components • Perform seamless top-level memory integration • Execute physical verification checks to ensure accuracy • Analyze IR drop and Electromigration issues

Requirements: • Bachelor’s/Master’s degree in Electrical/Electronics Engineering • Proven memory layout design experience at advanced technology nodes • Proficient with TSMC 7nm FinFET technology • Hands-on experience with industry layout tools • Robust problem-solving skills for debugging layout issues

Bring your advanced skills in memory layout and physical verification to make a real difference. #J-18808-Ljbffr

📌 Advanced Memory Layout Engineer Position (Montreal)
🏢 Odyssey Global
📍 Montreal