Join Infosys as a Technology Lead for Memory Layout, leveraging your design skills while working from Vancouver, BC. Collaborate with engineering teams on memory arrays and layout optimization.

This role requires a candidate with a solid background in Compiler and Memory Layout Design, taking schematic designs and enhancing layouts in cooperation with circuit teams. You will engage in high-performance design practices that make use of advanced technologies such as FinFET while ensuring compliance with DRC limitations.

This position provides a unique prospect to work on cutting-edge memory architectures.

Key Responsibilities:
Collaborate with engineers to optimize memory layout designs
Develop memory leafcell layout libraries from the ground up




Apply knowledge of various memory architectures
Ensure optimized layout design for enhanced performance
Perform physical verification and debug processes

Requirements:
Minimum 5 years of Compiler/Custom Memory Layout experience
Bachelor's degree or equivalent experience in a related field
Hands-on experience with Cadence Virtuoso and Calibre
Knowledge of 3nm and 5nm technologies
Must reside near Vancouver, BC, or relocate

Bring your expertise in memory layout and technology to drive success for Infosys in Vancouver.
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📌 Memory Layout Technology Lead At Infosys Burnaby
🏢 Infosys
📍 Burnaby