Senior Rtl/Fpga Design Eng - Verilog, Vivado, Cdc (Contract) - C$110 - C$135 An Hour (Varennes)

Senior Rtl/Fpga Design Eng - Verilog, Vivado, Cdc (Contract) - C$110 - C$135 An Hour (Varennes)

28 Aug
|
LanceSoft
|
Varennes

28 Aug

LanceSoft

Varennes

Seeking an experienced RTL/FPGA Design Engineer with expertise in Verilog, Vivado, and CDC for a contract role in the semiconductor industry. Requires 15+ years of experience and a Bachelor's degree.

📌 Senior Rtl/Fpga Design Eng - Verilog, Vivado, Cdc (Contract) - C$110 - C$135 An Hour (Varennes)
🏢 LanceSoft
📍 Varennes

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