Seeking a Senior ASIC Verification Engineer in Ottawa to verify large ASIC designs using SystemVerilog and UVM, requiring extensive experience in Verilog and SystemVerilog.
📌 Senior Asic Verification Engineer - Systemverilog/Uvm - C$120,000 - C$170,000 A Year (Boucherville)
🏢 Leading Technology Firm
📍 Boucherville
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