Digital Asic Design Engineer - C$109,000 - C$174,000 A Year (Varennes)

Digital Asic Design Engineer - C$109,000 - C$174,000 A Year (Varennes)

28 Aug
|
Ciena
|
Varennes

28 Aug

Ciena

Varennes

Design engineer role involving RTL and C code, focusing on power and area optimization for Wavelogic products, requiring experience with System Verilog and STA.

📌 Digital Asic Design Engineer - C$109,000 - C$174,000 A Year (Varennes)
🏢 Ciena
📍 Varennes

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