Seeking a Senior ASIC Verification Engineer in Ottawa to verify large ASIC designs using SystemVerilog and UVM, requiring extensive experience in Verilog and SystemVerilog.
📌 Senior Asic Verification Engineer - Systemverilog/Uvm - C$120,000 - C$170,000 A Year (Varennes)
🏢 Leading Technology Firm
📍 Varennes
Reply to this offer
Impress this employer describing Your skills and abilities, fill out the form below and leave Your personal touch in the presentation letter.