Job DetailsIntel's AI SoC organization develops cutting‑edge products powering a wide range of AI applications, from edge devices to data center accelerators. If you are an engineer with robust technical and communication skills who thrives in a fast‑paced environment with abundant learning opportunities, you are the ideal candidate for this role. Join us to shape the future of AI hardware.Develop the logic design, register transfer level (RTL) coding, and simulation for an SoC design and integrate logic of IP blocks and subsystems into a full chip SoC or discrete component design. Participate in the definition of architecture and micro‑architecture features of the block being designed. Perform quality checks in various logic design aspects ranging from RTL to timing/power convergence. Apply various strategies, tools, and methods to write RTL and optimize logic to qualify the design to meet power, performance, area, and timing goals as well as design integrity for physical implementation. Review the verification plan and implementation to ensure design features are verified correctly and resolve and implement corrective measures for failing RTL tests to ensure correctness of features. Follow secure development practices to address the security threat model and security objects within the design. Work with IP providers to integrate and validate IPs at the SoC level. Drive quality assurance compliance for smooth IP‑SoC handoff.ResponsibilitiesContribute to evaluation of architectural trade‑offs considering features, performance,



and system constraints.Implement RTL in Verilog/SystemVerilog based on defined micro‑architecture; integrate IP blocks at top level and ensure synthesis‑ and timing‑clean design.Work closely with verification teams to achieve full coverage and robust validation.Develop timing constraints for IP blocks and assist physical design teams with synthesis, timing closure, and formal equivalence checks.Support silicon bring‑up and post‑silicon validation activities, including debug and performance analysis.Collaborate with senior engineers to adopt best practices and improve design methodologies.QualificationsMinimum qualifications are required to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.Minimum QualificationsBachelor's degree in Electrical Engineering, Computer Engineering, or Computer Science.3+ years of experience in/with RTL design and implementation for ASIC/SoC development.Proficiency in Verilog/SystemVerilog for RTL coding and design.Experience with synthesis tools and timing closure methodologies.Preferred QualificationsUnderstanding of clock domain crossings, power optimization, and timing closure.Exposure to SoC system integration and CPU subsystem design.Familiarity with standard bus protocols (AXI, AHB, etc.) and embedded processor architectures.Knowledge of high‑speed and low‑power design techniques.Experience with static timing analysis (STA) tools and methodologies.Hands‑on experience with formal verification tools and techniques.Basic scripting skills (Python, TCL, etc.) for automation.Experience with EDA tools: HDL simulators (VCS, Questa, IES), lint tools (Spyglass),



and FPGA prototyping tools.Job TypeExperienced HireShiftShift 1 (Canada)Primary LocationCanada, TorontoBusiness GroupAt the Data Center Group (DCG), we're committed to delivering exceptional products and delighting our customers. We offer both broad‑market Xeon‑based solutions and custom x86‑based products, ensuring tailored innovation for diverse needs across general‑purpose compute, web services, HPC, and AI‑accelerated systems. Our charter encompasses defining business strategy and roadmaps, product management, developing ecosystems and business opportunities, delivering strong financial performance, and reinvigorating x86 leadership. Join us as we transform the data center segment through workload‑driven leadership products and close collaboration with our partners.Posting StatementAll qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation or any other characteristic protected by local law, regulation, or ordinance.Position of TrustN/AAnnual Salary Range for jobs which could be performed in CanadaCAD 109,380.00 – 154,420.00Work Model for this RoleThis role will be eligible for our hybrid work model which allows employees to split their time between working on‑site at their assigned Intel site and off‑site. Job posting details (such as work model, location or time type) are subject to change.Canada AccommodationIntel is committed to a culture of accessibility. Intel provides accommodations to applicants and employees with disabilities. Find information and request accommodation here.#J-18808-Ljbffr

📌 Design Engineer – Ai Soc Development - C$109,380 - C$154,420 A Year (Winnipeg)
🏢 Intel
📍 Winnipeg