Explore a rewarding role as a Lead ASIC Verification Engineer, where your skills in System Verilog and UVM will drive the development of advanced digital ASICs. Work within a diverse, cooperative team to achieve verification excellence. The ideal candidate will possess significant experience in ASIC verification, leading efforts to define, develop, and implement rigorous test methodologies.

Your responsibilities will encompass the creation of a verification framework and executing comprehensive test plans tailored to functional requirements. Key Responsibilities:
Lead development of advanced ASIC verification infrastructure
Create traffic generators in System Verilog and UVM
Develop and execute functional test plans
Define and run self-checking tests for digital ASICs Requirements:
Bachelor’s in computer science or electrical engineering, Master’s preferred
Over 8 years in ASIC verification
Experience developing test plans at sub-chip levels
Proficient in System Verilog and scripting languages
Solid grasp of UVM methodology Empower your career by making a significant impact in ASIC verification through this influential position.

📌 Lead Asic Verification Engineer Opportunity Quebec (Canada)
🏢 Myticas Consulting
📍 Canada