Seeking a Design Verification Engineer to evaluate AI model training for chip design, implement RTL components using Verilog/SystemVerilog, and develop ASIC design flows. Must have 3-10 years of experience and robust proficiency in Verilog/SystemVerilog and UVM.
📌 Design Verification Engineer - $100 - $149 An Hour - Remote (Toronto)
🏢 Mercor
📍 Toronto
Reply to this offer
Impress this employer describing Your skills and abilities, fill out the form below and leave Your personal touch in the presentation letter.