Design engineer role involving RTL and C code, focusing on power and area optimization for Wavelogic products, requiring experience with System Verilog and STA.
📌 Digital Asic Design Engineer - C$109,000 - C$174,000 A Year (Boucherville)
🏢 Ciena
📍 Boucherville
Reply to this offer
Impress this employer describing Your skills and abilities, fill out the form below and leave Your personal touch in the presentation letter.