This role sits at the core of next-generation high-speed connectivity technologies powering data-intensive applications such as AI, data centers, 5G infrastructure, and autonomous systems. You will work on advanced SERDES system modeling and analysis, contributing to the design and optimization of ultra-high-speed wireline communication systems. In this highly technical environment, you will simulate, analyze, and refine behavioral models for complex analog and digital signal processing blocks that enable 100G+ PAM4 performance. The role combines deep theoretical understanding with hands-on simulation and algorithm development, often leveraging machine learning techniques for optimization. You will collaborate closely with silicon engineering teams to ensure system-level performance alignment between models and real silicon. This is a cutting-edge engineering role where precision, innovation, and analytical rigor directly influence the performance of global communication infrastructure.AccountabilitiesPerform behavioral channel simulation and analysis of high-speed wireline SERDES systems supporting 100G+ PAM4 standards.Model and analyze key analog and mixed-signal blocks such as transmitters, FFE, CTLE, DFE, and CDRs.Contribute to system architecture definition for SERDES links across multiple communication standards.Develop and deploy simulation and debugging tools to support analog and validation engineering teams.Work on optimization and machine learning-based approaches to improve chip performance and efficiency.Design and refine adaptation algorithms for advanced equalization techniques.Conduct sensitivity analysis and regression simulations under varying link conditions.Collaborate with silicon engineering teams to correlate behavioral models with actual silicon performance.RequirementsMaster’s or PhD in Electrical Engineering, Computer Engineering, or Engineering Science.5+ years of experience in SERDES system design, modeling, or related high-speed communication systems.Solid experience modeling SERDES building blocks such as FFE, CTLE, DFE, CDR, and transmitter architectures.Proficiency in programming and scripting languages including MATLAB, C/C++, Python, Tcl, or Perl.Experience with PCIe and/or Ethernet SERDES specifications.Strong analytical mindset with excellent attention to detail and problem-solving skills.Strong communication skills and ability to collaborate across multidisciplinary engineering teams.Nice to have: experience with IBIS-AMI modeling.Nice to have: familiarity with industry standards such as PCI-SIG, IEEE 802.3, and OIF.BenefitsCompetitive base salary ranging from $115K to $225K depending on role level and experience.Additional compensation opportunities including RSUs, short-term incentives, and employee stock purchase plan (ESPP).Comprehensive health coverage and wellness programs.Health Spending Account (HSA) and Wellness Spending Account (WSA).Employee Assistance Program (EAP).Flexible paid vacation and paid holidays.Parental leave top-up program.Strong focus on health, prevention, and work-life balance.Exposure to cutting-edge semiconductor and high-speed communication technologies.#J-18808-Ljbffr

📌 Systems Serdes Engineer - $115,000 - $225,000 A Year (Winnipeg)
🏢 Jobgether
📍 Winnipeg