Be part of Celero's innovative team as a Senior ASIC Engineer focused on optical transceivers development in Ottawa, Ontario. Utilize your digital design skills for groundbreaking technology.
You will play a pivotal role in creating designs for next-generation optical modems. The ideal candidate holds a Bachelor's or higher in Electrical Engineering with three years of hands-on experience in ASIC design. You will engage in synthesis, timing analysis, and optimize designs while collaborating effectively with cross-functional teams.
Key Responsibilities:
• Design and implement digital circuits via HDL
• Conduct synthesis, timing analysis, and Clock Domain Crossing analysis
• Optimize ASIC designs focusing on performance and area
• Ensure design functionality through RTL simulations
• Collaborate in design reviews and team guidance
Requirements:
• Degree in Electrical or Computer Engineering
• Over 3 years of digital design experience required
• Expertise in Verilog/System Verilog essential
• Robust understanding of ASIC methodologies
• Effective communicator and problem solver
Elevate the standards of optical technology with your engineering skills at Celero.
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