Explore a rewarding role as a Lead ASIC Verification Engineer, where your skills in System Verilog and UVM will drive the development of advanced digital ASICs. Work within a diverse, cooperative team to achieve verification excellence.The ideal candidate will possess significant experience in ASIC verification, leading efforts to define, develop, and implement rigorous test methodologies. Your responsibilities will encompass the creation of a verification framework and executing comprehensive test plans tailored to functional requirements.Key Responsibilities:Lead development of advanced ASIC verification infrastructureCreate traffic generators in System Verilog and UVMDevelop and execute functional test plansDefine and run self-checking tests for digital ASICsRequirements:Bachelor's in computer science or electrical engineering, Master's preferredOver 8 years in ASIC verificationExperience developing test plans at sub-chip levelsProficient in System Verilog and scripting languagesStrong grasp of UVM methodologyEmpower your career by making a significant impact in ASIC verification through this influential position.#J-18808-Ljbffr