Job TitleSoC Validation Engineer — Pre-Silicon & Post-SiliconSummaryWe are looking for an experienced SoC Validation Engineer to drive end-to-end validation of complex System-on-Chip (SoC) designs across both pre-silicon and post-silicon phases. The ideal candidate brings deep domain expertise in SoC IP subsystems — including Clock, Reset, Ethernet, I/O controllers, and related infrastructure IPs — with proven ability to develop test strategies, execute validation plans, and root-cause failures from simulation through first silicon and production.Key ResponsibilitiesPre-Silicon ValidationDevelop comprehensive verification and validation plans for SoC-level IP subsystems including Clock Generation/Distribution (PLLs, clock muxes, dividers), Reset Architecture, Ethernet MAC/PHY, and I/O interfaces (GPIO, I2C, SPI, UART, JTAG)Create and execute directed and constrained-random tests targeting IP integration, connectivity, and functional correctness at the SoC levelVerify clock domain crossings (CDC), reset sequencing, and power-on reset (POR) behaviorValidate Ethernet data path integrity, link negotiation, and MAC-to-PHY (MII/RGMII/SGMII) interfacesPerform functional coverage analysis and drive coverage closure across IP blocksCollaborate with design and architecture teams on RTL debug, assertions, and specification reviewsExecute validation on emulation/FPGA prototyping platforms (Palladium, Veloce, Protium) for early software/firmware integrationPost-Silicon ValidationBring up and validate SoC IPs on first silicon and platform boardsDevelop and execute post-silicon test plans covering:Clock: PLL lock times, frequency accuracy, jitter characterization, clock switching,



glitch-free mux transitionsReset: Reset assertion/de-assertion sequencing, warm/cold reset flows, watchdog timer resets, brown-out detectionEthernet: Link bring-up, auto-negotiation, packet integrity (CRC/FCS), throughput/latency, loopback testing, PTP/IEEE 1588 timestampingI/O: Pin mux configuration, drive strength, voltage levels, protocol compliance (I2C/SPI/UART timing), interrupt routingDebug silicon failures using oscilloscopes, logic analyzers, protocol analyzers, JTAG/DFx, and embedded trace toolsPerform root-cause analysis of post-silicon bugs and drive resolution with design and firmware teamsCharacterize IP performance under varying voltage, frequency, and temperature (VFT) conditionsDevelop and maintain automated test frameworks for regression and production testingCollaborate with platform, firmware, BSP, and driver teams on system-level integration and debugGeneralAuthor and maintain validation documentation: test plans, debug reports, coverage metrics, and known-issue databasesDevelop Python/Perl/Tcl scripts for test automation, log parsing, and result analysisParticipate in silicon bring-up triage, failure analysis, and bug review meetingsMentor junior engineers and drive process improvements in validation methodologyInterface with IP vendors for third‐party IP integration, compliance, and issue resolutionRequired QualificationsEducation: B.S./M.S./Ph.D. in Electrical Engineering, Computer Engineering, or related fieldExperience: 4–10+ years in SoC validation (pre‐silicon and/or post‐silicon)Deep understanding of SoC architecture and IP integration conceptsTwitter LinkedIn Facebook Google+ Pinterest email #J-18808-Ljbffr

📌 Validation Engineer - Hcltech (North Vancouver)
🏢 Bilinguallink
📍 North Vancouver