Qualcomm Canada ULC seeks a Design Verification Engineer to join its memory subsystem verification team. You will develop verification strategies for memory controllers, DDR/LPDDR/HBM interfaces, and PHY logic, and drive functional and code coverage closure.
The candidate should have hands-on Verilog, SystemVerilog, UVM and SVA experience, and a robust interest in LPDDR, DDR, and HBM technologies, collaborating with RTL, architecture, and modeling teams.