- Constraint: This role is strictly ineligible for visa sponsorship.

Job Overview Our client is a leading global semiconductor company developing high-performance compute and connectivity solutions across client, server, data-center, graphics, embedded, and semi-custom platforms.

They are currently looking for an experienced ASIC Design Engineer to join a specialized engineering team responsible for complex I/O connectivity and virtualization IP used across multiple SoC product families.

This is a hands-on design role with broad ownership across the ASIC development cycle. The successful engineer will contribute from architectural requirements and RTL implementation through synthesis, design sign-off, timing closure support, and final integration into the SoC environment.

The position requires an engineer who can operate effectively across IP design, SoC integration, verification, synthesis, and physical-design teams rather than working exclusively within RTL development.

Key Responsibilities

- Translate architectural, functional, and performance requirements into robust RTL and microarchitecture.
- Design and implement complex digital IP using Verilog and SystemVerilog.
- Own assigned IP blocks through development, validation, sign-off, and SoC delivery.
- Drive synthesis and analyze timing, area, power, and implementation quality.
- Execute and close RTL lint, CDC/RDC, synthesis, and logical equivalence checking.




- Investigate and resolve synthesis, timing, constraint, and physical implementation issues.
- Work closely with SoC and physical-design teams to ensure successful integration and downstream consumption of the IP.
- Define and review clocks, resets, timing constraints, and key implementation assumptions.
- Debug complex issues spanning RTL, synthesis, CDC, LEC, timing, and SoC integration.
- Evaluate IP readiness and support final quality sign-off prior to SoC integration.
- Communicate technical risks, status, dependencies, and proposed solutions to geographically distributed engineering teams.
- Support project planning, effort estimation, and engineering resource requirements.
- Provide hands-on technical guidance to junior engineers when required.

Required Qualifications

- Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, Computer Science, or a related discipline.
- Robust professional experience in ASIC or SoC design.
- Proven hands-on RTL design experience on large-scale semiconductor projects.
- Strong Verilog and SystemVerilog skills.
- Strong debugging and root-cause analysis skills.
- Ability to independently drive technical tasks from definition through completion.
- Strong written and verbal communication skills.

Pay: $120,000.00-$160,000.00 per year Work Location: Hybrid remote in Vancouver, BC

📌 Principal ASIC Design & SoC Integration Engineer (Vancouver)
🏢 iC Consult
📍 Vancouver