Avanciers is seeking a highly skilled Layout design engineer to join our team for an full time position with one of our esteemed clients, based in Burnaby, BC, Canada Job Overview

- Job Title: Memory Layout Design Engineer
- Location: Burnaby, British Columbia, Canada (Commuting distance or willing to relocate)

Role & Responsibilities
- Layout & Design: Work on Registers, Memory Arrays, and Memory data path layout and design.
- Collaboration: Take schematics provided by the circuit team and collaborate with them to create the best layout possible.
- Library Creation: Design Memory Leafcell layout libraries from scratch, including top-level integration.

Required Qualifications & Experience Education & General Experience

- Degree: Bachelor s degree (or foreign equivalent) from an accredited institution. (3 years of progressive specialty experience can be considered in lieu of every 1 year of education).
- IT Experience: At least 4 years of experience in the technology sector.




- Physical Demands: Ability to sit and work at a computer for extended periods; effective communication via telephone, email, and face-to-face.

Core Technical Skills (5+ Years Required)
- Domain Expertise: Strong background in Compiler / Custom Memory Layout design and deep knowledge of different memory architectures.
- Advanced Silicon Nodes: Sound hands-on knowledge of FinFET technology, layout design, and DRC limitations with specific exposure to 3nm and 5nm nodes.
- Industry Tools: High proficiency in Cadence Virtuoso layout editor and Calibre physical verification flow.
- Verification: Proficient in physical verification flow and debugging, including:

- DRC (Design Rule Checking)

- LVS (Layout Versus Schematic)

- ERC (Electrical Rule Checking)

- Boundary conditions

📌 Technology Lead Memory Team Layout (Burnaby)
🏢 Avanciers
📍 Burnaby