We are hiring a Memory Layout Engineer in Ottawa, Ontario, with in-depth knowledge of advanced-node technologies. This position emphasizes memory layout development and physical integration.
In this role, you will apply your skills to optimize layouts for multiple memory components, ensuring top-level integration within SoC solutions. You will perform physical verification and maintain quality control through DRC, LVS, and density checks. Additionally, you will conduct IR drop and electromigration analysis, working closely with design and process teams.
Key Responsibilities:
• Design and optimize layouts for various memory components
• Implement top-level integration in SoC projects
• Conduct physical verification and closure signoff
• Perform critical DRC,



LVS, and density verification
• Address IR drop and electromigration issues effectively
Requirements:
• Experience with TSMC technology nodes from 3nm to 7nm
• Robust grasp of memory architecture and design methodologies
• Educational background in Electrical/Electronics Engineering
• Effective debugging and analytical problem-solving skills
• Ability to commute to Ottawa for daily work
Utilize your expertise to impact advanced memory design in our Ottawa location.
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📌 Expert Memory Layout Engineer Needed (Ottawa)
🏢 Value Innovation Labs
📍 Ottawa